1. Field of the Invention
The present invention relates to such a control system comprising control means for controlling an entire system, and a plurality of input/output means controlled in response to a reset signal issued from the control means, in which the control system is equipped with a reset circuit for selecting whether or not the reset signal is outputted to the input/output means when the control means is brought into such a condition that this control means cannot control the input/output means.
2. Description of the Related Art
Conventionally, a basic arrangement of a control system such as a programmable controller is made of control means for controlling the overall system, input/output means for interfacing the control means with respect to an external input/output appliance, a power supply for supplying 5V to the control means and the input/output means, and a backplane for fixing the control means and the input/output means to connect signals between the means.
In the above-described control system, for instance, when a failure happens to occur in the control means or the control means recognizes certain malfunctions, the following two cases are conceivable. The case is that all of the outputs from the input/output means are to be cleared. Another case is that conditions occurred immediately before the malfunction are to be held.
For example, a case where all of the outputs from the input/output means are desired to be cleared might exist when controlling a machine in a line. An example of a case where all of the outputs from the input/output means are to be maintained, is a temperature control or air conditioning situation.
FIG. 9 is an example of a reset circuit in one conventional control system. The reset circuit is usable for the control means and input/output means when a failure occurs in or a malfunction is recognized by the control means. In the FIG. 9 system a failure or malfunction cans all of the output to be cleared.
In FIG. 9, reference numeral 71 indicates control means, reference numeral 72 shows an input/output means, and reference numeral 73 is a transistor for drawing a reset signal to the input/output means 72. when the control means 71 is operated under normal condition. Reference numeral 74 represents a reset signal which is outputted from the control means 71 and is wire or gated wired-OR-gated to all of the input/output means 72. Reference numeral 75 is a pull-up resistor, and reference numeral 76 shows an output holding circuit for holding data, which is constructed of a flip-flop.
Also, reference numeral 77 indicated in FIG. 9 is a 5V output (abbreviated as xe2x80x9cxcexa35Vxe2x80x9d hereinafter) where a voltage of 5V is defined when even one power supply among a plurality of power supplies of the overall system. Shown in FIG. 10, the 5V outputs of all of the power supplies employed in the control means and the input/output means are coupled with each other by diodes 78.
In the above-described circuit, when a software reset signal; a hardware reset signal, or a power-supply reset signal becomes xe2x80x9cLOWxe2x80x9d, the base of the transistor 73 becomes xe2x80x9cLOWxe2x80x9d, and the reset signal 74 becomes xe2x80x9cHIGHxe2x80x9d by way of the pull-up resistor 75. The output holding circuit 76 employed inside the input/output means 72 is thereby reset, and all of the outputs from the input/output means 72 are cleared.
Also, even when the power supply of the input/output means 72 is turned ON prior to turning-ON of the power supply of the control means 71, since 5V is defined as xcexa35V 77 by FIG. 10, the output holding circuit 76 employed in the input/output means 72 is brought into the reset condition by the pull-up resistor 75. Accordingly, there is no case that the output from the output holding circuit 76 becomes indefinite.
In the circuit disclosed in Japanese Laid-open Patent Application 5-303448, it is possible by the software process operation to select whether or not the input/output means is cleared when the control means is reset.
In this circuit, a latch circuit is employed to select the gate of the output buffer in the signal output circuit module into an active/inactive condition. The latch circuit is set by the software as to whether or not the resetting operation is valid, so that a selection can be made of whether the output is to be cleared or held when the control means is cleared.
The conventional control system is constituted by the above-described arrangement. In the case of the reset circuit example in FIG. 9, for instance, when the hardware reset signal is outputted, since the pull-up resistor 75 employed in the control means 71 becomes xe2x80x9cHIGHxe2x80x9d and thus all of the input/output means are cleared, the input/output means could not be held by employing the hardware of the same control means. As a consequence the reset circuit could not be used in the control system which holds the latest conditions of the input/output means when a malfunction is recognized.
Also, in another circuit example disclosed in Japanese Laid-open Patent Application No. 5-303448, the latch circuit for selecting the gate of the output buffer into the active/inactive state is required in all of the input/output means provided on the system. Accordingly, the hardware circuits of the input/output means become complex, and the total cost of the system would be increased in espacially when that more than several tens of input/output means are coupled to a single control means.
The present invention has been made to solve the above-described problems, and has an object to provide a low cost control system with the same hardware arrangement, while conditions of input/output means can be either clear or held when malfunction occur.
To solve the above problems according to the present invention there is provided a control system having a control means for controlling overall system, and a plurality of input/output means for interfacing control means to external input/output appliances, in which the plurality of input/output means are reset in response to a reset signal from the control means. The control means includes a switch for selecting whether or not the reset signal is outputted to to the input/output means, and a reset circuit for directly outputting a reset signal having an implication of xe2x80x9cHIGHxe2x80x9d to the input/output means when the control means is set to output the reset signal, and for not outputting the reset signal to the input/output means when the control means is set not to output the reset signal, thereby forcibly drawing the reset signal to xe2x80x9cLOWxe2x80x9d.
Another aspect of the present invention involves a control system having two sets of control means, one of which is a controlling system and the other control means constituting a waiting system. This embodiment also has a bus switching means for connecting a bus between the input/output means and any one of the two control means; the two control means and the bus switching means are connected to a backplane. Setting of the switch of the control means is herein invalidated and the reset signal is necessarily outputted to the bus switching means.
Another aspect of the present invention provides a control system with two sets of control means as described above; a bus switching means for selecting between the two sets of control means in response to reset signals derived from the two sets of control means; and a plurality of input/output means for interfacing the control means connected by the bus switching means, with external input/output appliances.
In this embodiment the control means includes: a switch for selecting whether or not the reset signal is outputted to the input/output means; and a reset circuit for directly outputting a reset signal having an implication of xe2x80x9cHIGHxe2x80x9d to the input/output means when the switch is set to output the reset signal, and for not outputting the reset signal to the input/output means when the switch is set not to output the reset signal, thereby forcibly drawing the reset signal to xe2x80x9cLOWxe2x80x9d.
Another aspect of the present invention is a control system includes: a reset circuit for outputting a reset signal to the input/output means when power supplies of the input/output means are turned ON under certain conditions. For example when the power supply of the control means is turned OFF or when any one of the power supplies of the plural input/output means is turned OFF, the power supply of the control means is recovered, and all of the power to supplies of said plural input/output means are recovered, so that the system can be controlled.
Furthers a reset circuit for outputting a reset signal to the input/output means when the power supply of the input/output means is turned ON in the case that the power supply of the input/output means is recovered from the power down condition.